Each power device typically comprises a chip of semiconductor material, on which one or more power components (e.g., power transistors—such as vertical structure MOS power transistors) are integrated, and a package wherein the chip is encapsulated for protecting it and allowing access to terminals thereof.
More particularly, each power component usually comprises a collection terminal (for example, a drain terminal of the power transistor) extending on a lower surface of the chip (that typically, in use, is orientated towards a support, such as a printed circuit board—or PCB—on which the power device is mounted), a source terminal (e.g., a source terminal of the power transistor) extending on an upper surface of the chip (typically opposite the lower surface), and a control terminal (for example, a gate terminal of the power transistor) extending on the upper surface of the chip too, typically surrounding the source terminal.
The package typically comprises an insulating body having contacts (or leads) that allows connecting the power device to external circuits. Each lead is electrically connected to a corresponding terminal of the chip; in particular, according to a typical implementation, the package comprises source leads (e.g., three) connected to the source terminal of the power transistor, a drain lead connected to the drain terminal and a gate lead connected to the gate terminal.
The power devices have limitations that preclude use thereof in some applications. As it is known, such limitations are substantially related to the presence of parasitism affecting a driving of the power transistor.
In particular, since the leads (as well as the terminals and other conductive elements—for example, heat-sinks) have to meet specific safety parameters of the power device (for example, surface distances—“creepage” distances—and/or air distances—“clearance” distances), they have specific shape and/or size and are appropriately spaced apart from each other. For this reason, typically the source, drain and gate leads at least partially face on, or in correspondence of, a same surface of the insulating body that in use is oriented towards the PCB (or mounting surface). This involves that the source terminal of the power transistor (on the upper surface of the chip) is connected to the corresponding source leads (on the mounting surface of the package) through a relatively long conductive path that defines a parasitic inductor.
In some operating conditions, such a parasitic inductor may cause long switching times to the power device, and hence high switching losses.
For example, this may happen when switching from a turning-on condition of the power transistor (condition wherein the power transistor, having the gate terminal at a higher voltage than the source terminal by at least one threshold voltage, i.e. overdrive voltage greater than zero, is crossed by a high current) to a turning-off condition (overdrive voltage lower than or equal to zero). In this case, in fact, a decrease of the voltage at the gate terminal causes a decrease of the current in the power transistor. The source terminal, for effect of the parasitic inductor and because of such current decrease, is initially subjected to a greater voltage decrease with respect to the source lead (thereby settling then to the voltage value of the latter); therefore, the overdrive voltage zeroes after a certain delay (depending on a transient time required by the parasitic inductor to settle the voltage at the source terminal to that of the source terminal), thereby causing a corresponding delay in the turning-off of the power transistor.